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1/12 ds.ST14C02C/9811v2 ST14C02C memory card ic 2 kbit (256 x 8) serial i2c bus eeprom n single supply voltage (3 v to 5.5 v) n two wire i 2 c serial interface n byte and multbyte write (up to 4 bytes) n page write (up to 8 bytes) n byte, random and sequential read modes n self-timed programming cycle n automatic address incrementing n enhanced esd/latch-up behavior n 1 million erase/write cycles (minimum) n 10 year data retention (minimum) description this device is an electrically erasable programma- ble memory (eeprom) fabricated with stmicroelectronicss high endurance, advanced polysilicon, cmos technology. this guarantees an endurance typically well above one million erase/write cycles, with a data retention of 10 years. the memory operates with a power supply as low as 3 v. the device is available in wafer form (either sawn or unsawn) and in micromodule form (on film). the memory is compatible with the i 2 c standard. this is a two wire serial interface that uses a bi-di- rectional data bus and serial clock. the memory carries a built-in 7-bit unique device type identifi- er code (1010000) in accordance with the i 2 c bus definition. only one memory can be attached to each i 2 c bus. figure 1. logic diagram ai01162 scl v cc ST14C02C gnd sda mode table 1. signal names sda serial data/address input/ output scl serial clock mode write mode v cc supply voltage gnd ground micromodule (d15) wafer 2 2 2 2 micromodule (d20)
ST14C02C 2/12 figure 2. d15 contact connections ai02492 v cc gnd scl sda figure 3. d20 contact connections ai02491 v cc gnd scl sda mode the memory behaves as a slave device in the i 2 c protocol, with all memory operations synchronized by the serial clock. read and write operations are initiated by a start condition, generated by the bus master. the start condition is followed by the device select code which is composed of a stream of 7 bits (1010000), plus one read/write bit (r/w ) and is terminated by an acknowledge bit. when writing data to the memory, the memory in- serts an acknowledge bit during the 9 th bit time, following the bus masters 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a stop condition after an ack for write, and af- ter a noack for read. power on reset: v cc lock-out write protect in order to prevent data corruption and inadvertent write operations during power up, a power on re- set (por) circuit is included. the internal reset is held active until the v cc voltage has reached the por threshold value, and all operations are dis- abled C the device will not respond to any com- mand. in the same way, when v cc drops from the operating voltage, below the por threshold value, all operations are disabled and the device will not respond to any command. a stable and valid v cc must be applied before applying any logic signal. table 2. absolute maximum ratings 1 note: 1. except for the rating operating temperature range, stresses above those listed in the table absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and operation of the device at these or any other conditio ns above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi - tions for extended periods may affect device reliability. refer also to the st sure program and other relevant quality document s. 2. mil-std-883c, 3015.7 (100 pf, 1500 w ) 3. eiaj ic-121 (condition c) (200 pf, 0 w ) symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature wafer form module form -65 to 150 -40 to 120 c v io input or output range -0.3 to 6.5 v v cc supply voltage -0.3 to 6.5 v v esd electrostatic discharge voltage (human body model) 2 4000 v electrostatic discharge voltage (machine model) 3 500 v
3/12 ST14C02C figure 4. maximum r l value versus bus capacitance (c bus ) for an i 2 c bus ai01100 v cc c bus sda r l master r l scl c bus 100 200 300 400 0 4 8 12 16 20 c bus (pf) r l max (k w ) v cc = 5v signal description serial clock (scl) the scl input pin is used to synchronize all data in and out of the memory. a pull up resistor can be connected from the scl line to v cc . (figure 4 in- dicates how the value of the pull-up resistor can be calculated). serial data (sda) the sda pin is bi-directional, and is used to trans- fer data in or out of the memory. it is an open drain output that may be wire-ored with other open drain or open collector signals on the bus. a pull up resistor must be connected from the sda bus to v cc . (figure 4 indicates how the value of the pull-up resistor can be calculated). mode (mode) the mode input may be driven dynamically. it must be held at: n v il or v ih for the byte write mode n v ih for multibyte write mode n v il for page write mode when unconnected, the mode input is internally read as a v ih (multibyte write mode). note that the voltages are cmos levels, and are not ttl com- patible. on the d15 micromodule, the mode pin is not connected to a contact. this pin is left floating on the silicon. this type of ST14C02C is always in its multibyte mode, and cannot be changed from this. device operation the memory device supports the i 2 c protocol, as summarized in figure 5. any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiv- er. the device that controls the data transfer is known as the master, and the other as the slave. a data transfer can only be initiated by the master, which will also provide the serial clock for synchro- nization. the memory device is always a slave de- vice in all communication. table 3. endurance and data retention device endurance (erase/write cycles) data retention (years) ST14C02C 1,000,000 10
ST14C02C 4/12 figure 5. i 2 c bus protocol scl sda scl sda sda start condition sda input sda change ai00792 stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition state. a stop condition terminates communica- tion between the memory and the bus master. a stop condition at the end of a read command forces the memory device into its standby state. a stop condition at the end of a write command triggers the internal eeprom write cycle. acknowledge bit (ack) an acknowledge signal is used to indicate a suc- cessful data transfer. the bus transmitter, either master or slave, will release the sda bus after sending 8 bits of data. during the 9 th clock pulse start condition start is identified by a high to low transition of the sda line while the clock, scl, is stable in the high state. a start condition must precede any data transfer command. the memory continuously monitors (except during a programming cycle) the sda and scl lines for a start condition, and will not respond unless one is given. stop condition stop is identified by a low to high transition of the sda line while the clock scl is stable in the high table 4. device select code 1 note: 1. the most significant bit, b7, is sent first. device code rw b7 b6 b5 b4 b3 b2 b1 b0 device select 1010000rw
5/12 ST14C02C figure 6. write mode sequences stop start byte write dev sel byte addr data in start page write dev sel byte addr data in 1 data in 2 ai01941 stop data in n ack ack ack r/w ack ack ack r/w ack ack period the receiver pulls the sda bus low to ac- knowledge the receipt of the 8 data bits. data input during data input, the memory device samples the sda bus signal on the rising edge of the clock, scl. for correct device operation, the sda signal must be stable during the clock low-to-high transi- tion, and the data must change only when the scl line is low. memory addressing to start communication between the bus master and the slave memory, the master must initiate a start condition. following this, the master sends 8 bits to the sda bus line (with the most significant bit first). these bits represent the device select code (7 bits) and a rw bit. the seven most significant bits of the device se- lect code are the device type identifier, according to the i 2 c bus definition. for the memory device, the seven bits are fixed at 1010000b (a0h), as shown in table 4. the 8 th bit is the read or write bit (rw ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the cor- responding memory gives an acknowledgment on the sda bus during the 9 th bit time. write operations the multibyte write mode is selected when the mode pin is at v ih , and the page write mode is selected when mode pin is at v il . the mode pin may be driven dynamically to cmos input levels. following a start condition, the master sends a device select code with the rw bit reset to 0. the memory device acknowledges this, and waits for a byte address. the 8-bit byte address allows access within a 256-byte memory address-space. after receipt of the byte address, the device again responds with an acknowledge bit. byte write in the byte write mode, the master sends one data byte, which is acknowledged by the memory, as shown in figure 6. the master then terminates the transfer by generating a stop condition. the write mode is independent of the state of the mode pin, as shown in table 5, which could be left floating if only this mode is to be used. howev- er this is not a recommended operating mode, as this pin has to be connected to either v ih or v il to minimize the stand-by current. multibyte write for the multibyte write mode, the mode pin must be held at v ih, as shown in table 5. the multibyte write mode can be started from any address in the memory. the master sends one, two, three or four bytes of data, which are each acknowledged by the memory. the transfer is terminated by the master generating a stop condition. the maxi- mum duration of the write cycle is t w =10 ms (as shown in table 8), except when bytes span across two rows. (that is, when they have different values for the 6 most significant address bits, a7-a2). the programming time is then doubled to a maximum of 20 ms. writing more than four bytes in the multi-
ST14C02C 6/12 byte write mode may modify data bytes in an ad- jacent row. (each row is 8 bytes long). however, the multibyte write can properly write up to eight consecutive bytes only if the first address is the first address of the row (the seven following bytes thereby being written to the seven following bytes of this same row). when not connected, the mode pin is internally pulled to 1 and the multibyte write option is se- lected. page write for the page write mode, the mode pin must be held at v il (as shown in table 5). the page write mode allows up to eight bytes to be written in a sin- gle write cycle, provided that they are all located in the same row. that is, the five most significant memory address bits (a7-a3) must be the same. the master sends between one and eight bytes of data, each of which are acknowledged by the memory. after each byte is transferred, the inter- nal byte address counter is incremented (this han- dles the three least significant address bits). care must be taken to avoid address counter roll-over, as this could result in data being overwritten. the transfer is terminated by the master generat- ing a stop condition. for any write mode, the generation by the master of the stop condition starts the internal memory program cycle. all in- puts are disabled until the completion of this cycle and the memory will not respond to any request. minimizing system delays by polling on ack during the internal write cycle, the memory discon- nects itself from the bus, and copies the data from its internal latches to the memory cells. the maxi- mum write time (t w ) is indicated in table 8, but the typical time is shorter. to make use of this, an ack polling sequence can be used by the master. the sequence, as shown in figure 7, is as follows: C initial condition: a write is in progress. C step 1: the master issues a start condition followed by a device select byte (first byte of the new instruction). C step 2: if the memory is busy with the internal write cycle, no ack will be returned and the master goes back to step 1. if the memory has terminated the internal write cycle, it responds with an ack, indicating that the memory is ready to receive the second part of the next in- struction (the first byte of this instruction having been sent during step 1). read operations read operations are independent of the state of the mode pin. on delivery, the memory content is set at all 1s (ffh). current address read the memory has an internal byte address counter. each time a byte is read, this counter is increment- ed. for the current address read mode, following a start condition, the master sends a device se- lect with the rw bit set to 1. the memory device acknowledges this, and outputs the byte ad- dressed by the internal byte address counter, as shown in figure 9. the counter is then increment- ed. the master must not acknowledge the byte output, and terminates the transfer with a stop condition. random address read a dummy write is performed to load the address into the address counter, as shown in figure 6. this is followed by another start condition from the master and the device select is repeated with the rw bit set to 1. the memory device acknowl- edges this, and outputs the byte addressed. the master must not acknowledge the byte output, and terminates the transfer with a stop condition. table 5. operating modes note: 1. x = v ih or v il . mode rw bit mode 1 bytes initial sequence current address read 1 x 1 start, device select, rw = 1 random address read 0 x start, device select, rw = 0, address 1 x 1 restart, device select, rw = 1 sequential read 1 x 3 1 similar to current or random mode byte write 0 x 1 start, device select, rw = 0 multibyte write 0 v ih 4 start, device select, rw = 0 page write 0 v il 8 start, device select, rw = 0
7/12 ST14C02C figure 7. write cycle polling flowchart using ack write cycle in progress ai02454 next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop proceed write operation proceed random address read operation send byte address first byte of instruction with rw = 0 already decoded by ST14C02C table 7. capacitance 1 (t a = 25 c, f = 100 khz) note: 1. sampled only, not 100% tested. symbol parameter test condition min. max. unit c in input capacitance (sda) 8 pf c in input capacitance (other pins) 6 pf t ns noise suppression time con- stant (scl & sda inputs) 100 400 ns table 6. ac measurement conditions input rise and fall times 20 ns input pulse voltages 0.2v cc to 0.8v cc input and output timing reference voltages 0.3v cc to 0.7v cc figure 8. ac testing input/output waveform ai00825 0.8v cc 0.2v cc 0.7v cc 0.3v cc
ST14C02C 8/12 figure 9. read mode sequences start dev sel * byte addr start dev sel data out 1 ai01942 data out n stop start current address read dev sel data out random address read stop start dev sel * data out sequential current read stop data out n start dev sel * byte addr sequential random read start dev sel * data out 1 stop ack r/w no ack ack r/w ack ack r/w ack ack ack no ack r/w no ack ack ack r/w ack ack r/w ack no ack sequential read this mode can be initiated with either a current address read or a random address read. how- ever, in this case the master does acknowledge the data byte output, and the memory continues to output the next byte in sequence. to terminate the stream of bytes, the master must not acknowledge the last byte output, and must generate a stop condition. the output data comes from consecu- tive byte addresses, with the internal byte address counter automatically incremented after each byte output. after the last memory address, the address counter will roll-over and the memory will contin- ue to output data from the start of the memory block. acknowledge in read mode in all read modes the memory waits for an ac- knowledgment during the 9 th bit time. if the master does not pull the sda line low during this time, the memory device terminates the data transfer and switches to its standby state.
9/12 ST14C02C table 8. ac characteristics (t a = 0 to 70 c; v cc = 3v to 5.5v) note: 1. for a restart condition, or following a write cycle. 2. in the multibyte write mode only, if the accessed bytes span over two consecutive 8-byte rows (that is, if the 6 most signifi cant address bits are not constant) the maximum programming time is doubled to 20 ms symbol alt. parameter ST14C02C unit min max t ch1ch2 t r clock rise time 1 s t cl1cl2 t f clock fall time 300 ns t dh1dh2 t r sda rise time 1 s t dl1dl2 t f sda fall time 300 ns t chdx 1 t su:sta clock high to input transition 4.7 s t chcl t high clock pulse width high 4 s t dlcl t hd:sta input low to clock low (start) 4 s t cldx t hd:dat clock low to input transition 0 s t clch t low clock pulse width low 4.7 s t dxcx t su:dat input transition to clock transition 250 ns t chdh t su:sto clock high to input high (stop) 4.0 s t dhdl t buf input high to input low (bus free) 4.7 s t clqv t aa clock low to data out valid 3.5 s t clqx t dh data out hold time after clock low 300 ns f c f scl clock frequency 100 khz t w 2 t wr write time 10 ms table 9. dc characteristics (t a = 0 to 70 c; v cc = 3v to 5.5v) symbol parameter test condition min. max. unit i li input leakage current 0v v in v cc 2 a i li input leakage current (mode pad) 0v v in v cc 10 a i lo output leakage current 0v v out v cc, sda in hi-z 2 a i cc supply current v cc = 5 v, f c = 100 khz (rise/fall time < 10 ns) 2ma i cc1 supply current (stand-by) v in = v ss or v cc , v cc = 5 v 100 a v il input low voltage (scl, sda) - 0.3 0.3 v cc v v ih input high voltage (scl, sda) 0.7 v cc v cc + 1 v v il input low voltage (mode) - 0.3 0.5 v v ih input high voltage (mode) v cc - 0.5 v cc + 1 v v ol output low voltage i ol = 3 ma, v cc = 5 v 0.4 v
ST14C02C 10/12 figure 10. ac waveforms scl sda in scl sda out scl sda in tchcl tdlcl tchdx start condition tclch tdxcx tcldx sda input sda change tchdh tdhdl stop & bus free data valid tclqv tclqx data output tchdh stop condition tchdx start condition write cycle tw ai00795b ordering information devices are shipped from the factory with the memory content set at all 1s (ffh). the notation used for the device number is as shown in table 10. for a list of available options (speed, package, etc...) or for further information on any aspect of this device, please contact the st sales office nearest to you. sawn wafers are scribed and mounted in a frame on adhesive tape. the orientation is defined by the position of the gnd pad on the die, viewed with active area of product visible, relative to the notch- es of the frame (as shown in figure 11). the orien- tation of the die with respect to the plastic frame notches is specified by the customer. one further concern, when specifying devices to be delivered in this form, is that wafers mounted on adhesive tape must be used within a limited pe- riod from the mounting date: C two months, if wafers are stored at 25c, 55% relative humidity C six months, if wafers are stored at 4c, 55% rel- ative humidity
11/12 ST14C02C table 10. ordering information scheme example: ST14C02C - d20 delivery form d15 module on super 35 mm film d20 module on super 35 mm film w2 unsawn wafer (275 m m 25 m m thickness) w4 unsawn wafer (180 m m 15 m m thickness) s2x sawn wafer (275 m m 25 m m thickness) s4x sawn wafer (180 m m 15 m m thickness) where x indicates the sawing orientation, as follows (and as shown in figure 11) 1 gnd at top right 2 gnd at bottom right 3 gnd at bottom left 4 gnd at top left figure 11. sawing orientation ai02171 1 orientation gnd gnd gnd gnd 234 view: wafer front side
ST14C02C 12/12 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. ? 199 9 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com

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